View CY14B104L_1130133.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
CY14B104L/CY14B104N
4-Mbit (512K x 8/256K x 16) nvSRAM
Feature
* 15 ns, 25 ns, and 45 ns access times * Internally organized as 512K x 8 or 256K x 16 * Hands-off automatic STORE on power down with only a small capacitor * STORE to QuantumTrap(R) nonvolatile elements is initiated by software, device pin or Autostore(R) on power down * RECALL to SRAM initiated by software or power up * Infinite read, write, and recall cycles * 8 mA typical ICC at 200 ns cycle time * 200,000 STORE cycles to QuantumTrap * 20 year data retention * Single 3V +20%, -10% operation * Commercial and industrial temperatures * FBGA and TSOP - II packages * RoHS compliance
Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K words of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
Logic Block Diagram VCC VCAP
Address A0 - A18
CE OE WE
DQ0 - DQ15 CY14B104L/CY14B104N
BHE BLE
HSB
VSS
Cypress Semiconductor Corporation Document #: 001-07102 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 29, 2007
[+] Feedback
PRELIMINARY
Pin Configurations 48 - FBGA
(x16)
CY14B104L/CY14B104N
Top View (not to scale)
1 BLE 2 OE 3 A0 A3 A5 4 A1 A4 A6 A7 5 A2 CE 6 NC DQ0 A B C D E F G H
DQ8 BHE DQ9 DQ10 VSS
DQ1 DQ2 DQ3 VCC VSS
DQ11 A17
VCC DQ12 VCAP DQ14 DQ13 A14 DQ15 HSB NC A8 A12 A9
A16 DQ4 A15 A13 A10
DQ5 DQ6 WE A11 DQ7 NC
A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 - TSOP II
(x16)
Top View (not to scale)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10
NC NC[1] A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 - TSOP II
(x8)
Top View (not to scale)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
HSB NC [1] NC A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
Note 1. Expandable to 8Mbit,16Mbit
Document #: 001-07102 Rev. *E
Page 2 of 21
[+] Feedback
PRELIMINARY
Pin Configurations (continued)
NC [1] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 54 - TSOP II 11 (x16) 12 13 Top View 14 (not to scale) 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB NC [1] A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC
CY14B104L/CY14B104N
Pin Definitions
Pin Name A0 - A16 IO Type Input Description Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
DQ0 - DQ7 Input Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. WE CE OE VSS VCC HSB Input Input Input Ground Write Enable Input, Active LOW. When selected LOW, enables data on the IO pins to be written to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. IO pins are tri-stated on deasserting OE high. Ground For The Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs To The Device. Input Output Hardware Store Busy (HSB). When low this output indicates a hardware store is in progress. When pulled low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected. (connection optional) Power Supply Autostore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect No Connect. Do not connect this pin to the die.
VCAP NC
Document #: 001-07102 Rev. *E
Page 3 of 21
[+] Feedback
PRELIMINARY
Device Operation
The CY14B104L/CY14B104N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel.During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14B104L/CY14B104N suports infinite reads and writes just like a typical SRAM.In addition,it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations.
CY14B104L/CY14B104N
Figure 1shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC Electrical Characteristics on page 8 for the size of VCAP. To reduce unnecessary nonvolatile stores, AutoStore, and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress. Figure 1. AutoStore Mode
V CC V CAP V CC
10k Ohm
SRAM Read
The CY14B104L/CY14B104N performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-18/A0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each will be accessed. When the read is initiated by an address transition, the outputs will be valid after a delay of tAA (read cycle #1). If the read is initiated by CE or OE, the outputs will be valid at tACE or at tDOE, whichever is later (read cycle #2). The data outputs will repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and will remain valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
V CAP
WE
V CC V CC V CAP
V CAP
SRAM Write
A WRITE cycle is performed whenever CE and WE are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common IO pins DQ0-15 will be written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. It is recommended that OE kept high during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left low, internal circuitry turns off the output buffers tHZWE after WE goes low.
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB pin for controlling and acknowledging the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven low, the CY14B104L/CY14B104N conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY14B104L/CY14B104N continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the CY14B104L/CY14B104N continues to drive the HSB pin low, releasing it only when the STORE is complete.
AutoStore Operation
The CY14B104L/CY14B104N stores data to nvSRAM using one of the three storage operations. These three operations are Hardware Store activated by HSB, Software Store activated by an address sequence, and AutoStore on device power down. AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104L/CY14B104N. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor.
Document #: 001-07102 Rev. *E
0.1UF
Page 4 of 21
0.1UF
[+] Feedback
PRELIMINARY
Upon completion of the STORE operation the CY14B104L/CY14B104N remains disabled until the HSB pin returns high. Leave the HSB unconnected if is not used.
CY14B104L/CY14B104N
4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled READs or OE controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle commences and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that OE be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and takes tHRECALL to complete.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B104L/CY14B104N software STORE cycle is initiated by executing sequential CE-controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If there are intervening READ or WRITE accesses, the sequence will be aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.
Document #: 001-07102 Rev. *E
Page 5 of 21
[+] Feedback
PRELIMINARY
Table 1. Mode Selection CE H L L L WE X H L H OE X L X L A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63
CY14B104L/CY14B104N
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall
IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power Standby Active Active Active [2,3,4]
L
H
L
Active [2,3,4]
L
H
L
Active ICC2 [2,3,4]
L
H
L
Active [2,3,4]
Preventing AutoStore
The AutoStore function can be disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore can be re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed
in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Notes 2. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 3. While there are 19 address lines on the CY14B104L/CY14B104N, only the lower 16 lines are used to control software modes. 4. IO state depends on the state of OE. The IO table shown assumes OE LOW.
Document #: 001-07102 Rev. *E
Page 6 of 21
[+] Feedback
PRELIMINARY
Data Protection
The CY14B104L/CY14B104N protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104L/CY14B104N is in a write mode (both CE and WE
CY14B104L/CY14B104N
low) at power up, after a RECALL, or after a STORE, the write will be inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY Application Note AN1064.
Document #: 001-07102 Rev. *E
Page 7 of 21
[+] Feedback
PRELIMINARY
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +150C Supply Voltage on VCC Relative to GND ......... -0.5V to 4.1V Voltage Applied to Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Input Voltage ............................................ -0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VCC + 2.0V
CY14B104L/CY14B104N
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds).......................................... +260C Output Short Circuit Current [5] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V 2.7V to 3.6V
Above table contains advanced information.
DC Electrical Characteristics
Parameter ICC1 Description Average VCC Current
[6] Over the Operating Range (VCC = 2.7V to 3.6V) Test Conditions tAVAV = 15 ns tAVAV = 25 ns tAVAV = 45 ns Dependent on output loading and cycle rate.Values obtained without output loads. IOUT = 0 mA All Inputs Don't Care, VCC = Max Average current for duration tSTORE Commercial Min Max 70 65 50 75 70 52 3 25 Unit mA mA mA mA mA mA mA mA
Industrial
ICC2 ICC3
Average VCC Current during STORE
Average VCC Current at WE > (VCC - 0.2). All other I/P cycling. tAVAV = 200 ns, 3V, Dependent on output loading and cycle rate. Values obtained 25C typical without output loads. Average VCAP Current All Inputs Don't Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. -1 -1 2.0 VCC - 0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V Rated 35 2.4 VCC = Max, VSS < VIN < VCC, CE or OE > VIH
ICC4 ISB
3 1
mA mA
IIX IOZ VIH VIL VOH VOL VCAP
Input Leakage Current VCC = Max, VSS < VIN < VCC Off-State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
+1 +1 VCC + 0.5 0.8 0.4 57
A A V V V V F
Capacitance [7]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max 7 7 Unit pF pF
Notes 5. Outputs shorted for no more than one second. No more than one output shorted at a time. 6. Typical conditions for the active current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 3V. Not 100% tested. 7. These parameters are guaranteed but not tested.
Document #: 001-07102 Rev. *E
Page 8 of 21
[+] Feedback
PRELIMINARY
[7] Thermal Resistance Parameter Description Test Conditions
CY14B104L/CY14B104N
48-FBGA 44-TSOP II 54-TSOP II TBD TBD TBD TBD TBD TBD
Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Thermal Resistance (Junction to Case)
AC Test Loads
R1 577 3.0V OUTPUT 30 pF R2 789 3.0V OUTPUT 5 pF R2 789 R1 577
for tri-state specs
Document #: 001-07102 Rev. *E
Page 9 of 21
[+] Feedback
PRELIMINARY
AC Test Conditions
Input Pulse Levels ................................................... 0V to 3V Input Rise and Fall Times (10% - 90%) ....................... <5 ns Input and Output Timing Reference Levels ....................1.5V
CY14B104L/CY14B104N
AC Switching Characteristics
Parameters Cypress Parameters tACE tRC[8] tAA[9] tDOE tOHA tLZCE
[10]
15ns Description Min Max
25ns Min Max
45ns Min. Max. Unit
Alt. Parameters tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW -
SRAM Read Cycle Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enale to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write 3 15 15 10 15 5 0 15 0 0 7 3 20 0 7 25 20 20 10 0 20 0 0 10 3 30 0 15 10 0 10 45 30 30 15 0 30 0 0 15 0 7 0 25 12 0 22 3 3 7 0 10 0 45 22 15 15 10 3 3 10 0 15 15 25 25 12 3 3 15 25 45 45 20 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tHZCE[10] tLZOE[10] tHZOE[10] tPU[7] tPD[7] tDBE tLZBE tHZBE tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE[10,11] tLZWE[10] tBW
SRAM Write Cycle
Notes 8. WE must be HIGH during SRAM read cycles. 9. Device is continuously selected with CE and OE both LOW. 10. Measured 200 mV from steady state output voltage. 11. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
Document #: 001-07102 Rev. *E
Page 10 of 21
[+] Feedback
PRELIMINARY
AutoStore/Power Up RECALL
Parameters tHRECALL [12] tSTORE
[13]
CY14B104L/CY14B104N
Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time
CY14B104L/CY14B104N Min Max 20 15 2.65 150
Unit ms ms V s
VSWITCH tVCCRISE
Software Controlled STORE/RECALL Cycle [14,15]
Parameters tRC tAS tCW tGHAX tRECALL tSS [16,17] Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 15ns Min 15 0 12 1 100 70 Max 25 0 20 1 100 70 25ns Min Max 45 0 30 1 100 70 45ns Min. Max. Unit ns ns ns ns s s
Hardware STORE Cycle
Parameters tDELAY [18] tHLHX Description Time allowed to complete SRAM Cycle Hardware STORE Pulse Width CY14B104L/CY14B104N Min 1 15 Max 70 Unit s ns
Switching Waveforms
Figure 2. SRAM Read Cycle #1: Address Controlled [8,9,19]
tRC
ADDRESS
t AA t OHA
DQ (DATA OUT) DATA VALID
Notes 12. tHRECALL starts from the time VCC rises above VSWITCH. 13. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE will take place. 14. The software sequence is clocked with CE controlled or OE controlled reads. 15. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles. 16. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 17. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command. 18. Read and write cycles in progress before HSB are supplied this amount of time to complete.
Document #: 001-07102 Rev. *E
Page 11 of 21
[+] Feedback
PRELIMINARY
Switching Waveforms (continued)
CY14B104L/CY14B104N
Figure 3. SRAM Read Cycle #2: CE and OE Controlled [8,19,21]
tRC
ADDRESS
tACE
CE
tLZCE
tPD tHZCE
OE
tDOE tLZOE
BHE , BLE
t HZOE
tLZBE
DQ (DATA OUT)
tDBE
DATA VALID
tHZCE tHZBE
t PU
ICC
STANDBY
ACTIVE
Figure 4. SRAM Write Cycle #1: WE Controlled [19,20,21]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE
tBW
BHE , BLE
tSD
DATA IN DATA VALID
tHD
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Document #: 001-07102 Rev. *E
Page 12 of 21
[+] Feedback
PRELIMINARY
Switching Waveforms (continued)
CY14B104L/CY14B104N
Figure 5. SRAM Write Cycle #2: CE Controlled[21]
tWC
ADDRESS
tSA
CE
tSCE tAW tHA tPWE
WE
BHE , BLE
tBW
tSD tHD
DATA VALID
DATA IN
DATA OUT
HIGH IMPEDANCE
Figure 6. AutoStore/Power Up RECALL
VCC VSWITCH
STORE occurs only if a SRAM write has happened
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
Document #: 001-07102 Rev. *E
Page 13 of 21
[+] Feedback
PRELIMINARY
Switching Waveforms (continued)
CY14B104L/CY14B104N
Figure 7. CE-controlled Software STORE/RECALL Cycle [15]
tRC tRC
ADDRESS ADDRESS ADDRESS ## 1 ADDRESS 1
tRC tRC
ADDRESS ## 6 ADDRESS 6
tSA tAS
CE CE
tSCE tCW
tGLAX tGHAX
OE OE
t t STORE/ /t t RECALL STORE RECALL
DQ (DATA) DQ (DATA) DATA VALID DATA VALID DATA VALID DATA VALID
HIGH IMPEDANCE HIGH IMPEDANCE
Figure 8. OE-controlled Software STORE/RECALL Cycle [15]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tAS
OE
tCW
tGHAX
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Document #: 001-07102 Rev. *E
Page 14 of 21
[+] Feedback
PRELIMINARY
Switching Waveforms (continued)
Figure 9. Hardware STORE Cycle[18]
CY14B104L/CY14B104N
Figure 10. Soft Sequence Processing[16,17]
tSS
tSS
Document #: 001-07102 Rev. *E
Page 15 of 21
[+] Feedback
PRELIMINARY
Ordering Information
Speed (ns) 15 Ordering Code CY14B104L-ZS15XCT CY14B104L-ZS15XIT CY14B104L-ZS15XI CY14B104L-ZSP15XCT CY14B104L-ZSP15XIT CY14B104L-ZSP15XI CY14B104N-BA15XCT CY14B104N-BA15XIT CY14B104N-BA15XI CY14B104N-ZS15XCT CY14B104N-ZS15XIT CY14B104N-ZS15XI CY14B104N-ZSP15XCT CY14B104N-ZSP15XIT CY14B104N-ZSP15XI 25 CY14B104L-ZS25XCT CY14B104L-ZS25XIT CY14B104L-ZS25XI CY14B104L-ZSP25XCT CY14B104L-ZSP25XIT CY14B104L-ZSP25XI CY14B104N-BA25XCT CY14B104N-BA25XIT CY14B104N-BA25XI CY14B104N-ZS25XCT CY14B104N-ZS25XIT CY14B104N-ZS25XI CY14B104N-ZSP25XCT CY14B104N-ZSP25XIT CY14B104N-ZSP25XI Package Diagram 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85128 51-85128 51-85128 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85128 51-85128 51-85128 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160
CY14B104L/CY14B104N
Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II
Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Notes 19. HSB must remain HIGH during READ and WRITE cycles. 20. CE or WE must be > VIH during address transitions. 21. BHE and BLE are applicable for x16 configuration only.
Document #: 001-07102 Rev. *E
Page 16 of 21
[+] Feedback
PRELIMINARY
Ordering Information (continued)
Speed (ns) 45 Ordering Code CY14B104L-BV45XCT CY14B104L-BV45XIT CY14B104L-BV45XI CY14B104L-ZS45XCT CY14B104L-ZS45XIT CY14B104L-ZS45XI CY14B104L-ZSP45XCT CY14B104L-ZSP45XIT CY14B104L-ZSP45XI CY14B104N-BV45XCT CY14B104N-BV45XIT CY14B104N-BV45XI CY14B104N-ZS45XCT CY14B104N-ZS45XIT CY14B104N-ZS45XI CY14B104N-ZSP45XCT CY14B104N-ZSP45XIT CY14B104N-ZSP45XI Package Diagram 51-85128 51-85128 51-85128 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85128 51-85128 51-85128 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160
CY14B104L/CY14B104N
Package Type 48-ball FBGA 48-ball FBGA 48-ball FBGA 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II
Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Document #: 001-07102 Rev. *E
Page 17 of 21
[+] Feedback
PRELIMINARY
CY14B104L/CY14B104N
PART NUMBERING NOMENCLATURE CY 14 B 104 L - ZS P 15 X C T
Option: T - Tape & Reel Blank - Std.
Pb-Free P - 54 Pin Blank - 44 Pin Package: BA - 48 FBGA ZS - TSOP II
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
Speed: 15 - 15 ns 25 - 25 ns 45 - 45 ns
Data Bus: L - x8 N - x16
Voltage: B - 3.0V
Density: 104 - 4 Mb
NVSRAM 14 - AutoStore + Software Store + Hardware Store
Cypress
Document #: 001-07102 Rev. *E
Page 18 of 21
[+] Feedback
PRELIMINARY
Package Diagrams
Figure 11. 54-pin TSOP II (51-85160)
CY14B104L/CY14B104N
51-85160-**
Figure 12. 44-Pin TSOP II (51-85087)
MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
Document #: 001-07102 Rev. *E
Page 19 of 21
[+] Feedback
PRELIMINARY
Package Diagrams (continued)
CY14B104L/CY14B104N
Figure 13. 48-ball FBGA (6 mm x 10 mm x 1.2 mm)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C
A B C
10.000.10
10.000.10
0.75
5.25
D E F G H
D E
2.625
F G H
A B 6.000.10
A
1.875 0.75 3.75
0.530.05
0.25 C
B
6.000.10
0.210.05
0.15 C
0.15(4X)
SEATING PLANE
0.36
C
1.20 MAX
51-85128-*D
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-07102 Rev. *E
Page 20 of 21
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
PRELIMINARY
Document History Page
Document Title: CY14B104L/CY14B104N 1-Mbit (128K x 8) nvSRAM Document Number: 001-07102 REV. ** *A ECN NO. 431039 489096 Issue Date See ECN See ECN Orig. of Change TUP TUP New Data Sheet
CY14B104L/CY14B104N
Description of Change
Removed 48 SSOP Package Added 48 FBGA and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform Removed 35 ns speed bin Added 55 ns speed bin. Updated AC table for the same Changed "Unlimited" read/write to "infinite" read/write Features section: Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles Shaded Commercial grade in operating range table Modified Icc/Isb specs 48 FBGA package nomenclature changed from BW to BV Modified part nomenclature table. Changes reflected in the ordering information table Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35F Changed VIH max to Vcc + 0.5V Changed tSTORE to 15ms Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min specification for Vswitch Changed tGLAX to 1ns Added tDELAY max of 70us Changed tSS specification from 70us min to 70us max Changed the datasheet from Advance information to Preliminary 48 FBGA package code changed from BV to BA Removed 48 FBGA package in X8 configuration in ordering information. Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW in 15ns part to15ns Changed A18 and A19 Pins in FBGA Pin Configuration to NC Included all the information for 45ns part in this datasheet
*B
499597
See ECN
PCI
*C
517793
See ECN
TUP
*D
774001
See ECN
UHA
*E
914220
See ECN
UHA
Document #: 001-07102 Rev. *E
Page 21 of 21
[+] Feedback

▲Up To Search▲

Price & Availability of CY14B104L

	To Download CY14B104L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .